M48T02
M48T12
16 Kbit (2Kb x8) TIMEKEEPER
SRAM
November 1998 1/15
INTEGRATED ULTRALOW POWER SRAM,
REAL TIME CLOCK and POWER-FAIL
CONTROLCIRCUIT
BYTEWIDE RAM-LIKECLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
TYPICALCLOCK ACCURACY of
±
1 MINUTE
a MONTH, AT 25°C
SOFTWARE CONTROLLED CLOCK
CALIBRATIONfor HIGH ACCURACY
APPLICATIONS
AUTOMATICPOWER-FAILCHIP DESELECTand
WRITE PROTECTION
WRITEPROTECT VOLTAGES
(V
PFD
= Power-fail DeselectVoltage):
– M48T02: 4.5V
≤
V
PFD
≤
4.75V
– M48T12: 4.2V
≤
V
PFD
≤
4.5V
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Kb x8 SRAMs
DESCRIPTION
The M48T02/12TIMEKEEPER
RAM is a 2Kb x8
non-volatile static RAM and real time clock which
is pin and functional compatible with the DS1642.
A special 24 pin 600mil DIP CAPHAT
package
housesthe M48T02/12silicon with a quartzcrystal
and a long life lithium button cell to form a highly
integratedbatterybacked-upmemoryandrealtime
clock solution.
AI01027
11
A0-A10
W
DQ0-DQ7
V
CC
M48T02
M48T12
G
V
SS
8
E
Figure 1. Logic Diagram
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
24
1
PCDIP24 (PC)
Battery/Crystal CAPHAT
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature 0 to 70 °C
T
STG
Storage Temperature (V
CC
Off, Oscillator Off) –40 to 85
°
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds 260 °C
V
IO
Input or Output Voltages –0.3 to 7 V
V
CC
Supply Voltage –0.3 to 7 V
I
O
Output Current 20 mA
P
D
Power Dissipation 1 W
Notes: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 2. Absolute Maximum Ratings
(1)
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X X High Z Standby
Write V
IL
XV
IL
D
IN
Active
Read V
IL
V
IL
V
IH
D
OUT
Active
Read V
IL
V
IH
V
IH
High Z Active
Deselect V
SO
to V
PFD
(min) X X X High Z CMOS Standby
Deselect
≤
V
SO
X X X High Z Battery Back-up Mode
Notes:X=V
IH
or V
IL
;V
SO
= Battery Back-up Switchover Voltage.
Table 3. Operating Modes
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
A8
A9
DQ7
W
G
E
DQ5DQ1
DQ2
DQ3V
SS
DQ4
DQ6
V
CC
AI01028
M48T02
M48T12
8
1
2
3
4
5
6
7
9
10
11
12
16
15
24
23
22
21
20
19
18
17
14
13
Figure 2. DIP Pin Connections
The M48T02/12 button cell has sufficient capacity
andstoragelife tomaintaindataandclockfunction-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperaturerange.
The M48T02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2Kb x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
AsFigure 3 shows,the staticmemoryarray and the
quartzcontrolled clock oscillatorof the M48T02/12
are integratedon one silicon chip. The two circuits
are interconnected at the upper eight memory lo-
cations to provide user accessible BYTEWIDE
clockinformationin thebyteswithaddresses7F8h-
7FFh.The clock locationscontainthe year,month,
date,day,hour,minute,andsecondin 24hourBCD
format. Corrections for 28, 29 (leap year), 30, and
31 day months are made automatically.
DESCRIPTION (cont’d)
2/15
M48T02, M48T12
AI01019
5V
OUT
C
L
= 100pF
C
L
includes JIG capacitance
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤
5ns
Input Pulse Voltages 0V to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01329
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
V
PFD
V
CC
V
SS
32,768
Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
2040 x
8
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
POWER
BOK
Figure 3. Block Diagram
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT
read/write memory cells.
The M48T02/12 includes a clock control circuit
which updatestheclockbyteswithcurrentinforma-
tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
TheM48T02/12also hasits own Power-fail Detect
circuit. The controlcircuitryconstantlymonitorsthe
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protectstheSRAM,providingahigh degreeof data
security in the midst of unpredictable system op-
eration brought on by low V
CC
.AsV
CC
falls below
approximately3V,the controlcircuitryconnectsthe
battery which maintains data and clock operation
until valid power returns.
3/15
M48T02, M48T12
